PDF《USB 3.0 xHCI HOST CONTROLLER》

57 4.62 General Control

1 Register

58 4.63 General Control

2 Register

59 4.64 USB Control Register

59 4.65 De-Emphasis and Swing Control Register

61 4.66 Equalizer Control Register

62 4.67 Custom PHY Transmit/Receive Control Register

63 5 PCI EXPRESS EXTENDED CONFIGURATION SPACE

65 5.1 The PCI Express Extended Configuration Map

65 5.2 Advanced Error Reporting capability Register

65 5.3 Next Capability Offset / Capability Version Register

66 5.4 Uncorrectable Error Status Register

66 5.5 Uncorrectable Error Mask Register

67 5.6 Uncorrectable Error Severity Register

68 5.7 correctable Error Severity Register

69 5.8 correctable Error Mask Register

70 5.9 Advanced Error Capabilities and control Register

71 5.10 Header Log Register

72 5.11 Device Serial Number Capability ID Register

72 5.12 Next Capability Offset/Capability Version Register

72 5.13 Device Serial Number Register

73 6 xHCI MEMORY MAPPED REGISTER SPACE

74 6.1 The xHCI Register Map

74 Copyright ? 2011C2013, Texas Instruments Incorporated Contents

3 TUSB7320, TUSB7340 SLLSE76L CMARCH 2011CREVISED MAY

2013 www.ti.com 6.2 Host Controller Capability Registers

74 6.2.1 Capability Registers Length

74 6.2.2 Host Controller Interface Version Number

75 6.2.3 Host Controller Structural Parameters

1 75 6.2.4 Host Controller Structural Parameters

2 76 6.2.5 Host Controller Structural Parameters

3 76 6.2.6 Host Controller Capability Parameters

77 6.2.7 Doorbell Offset

78 6.2.8 Runtime Register Space Offset

78 6.3 Host Controller Operational Registers

79 6.3.1 USB Command Register

79 6.3.2 USB Command Register

80 6.3.3 USB Status Register

80 6.3.4 Page Size Register

81 6.3.5 Device Notification Control Register

82 6.3.6 Command Ring Control Register

82 6.3.7 Device Context Base Address Array Pointer Register

83 6.3.8 Configure Register

84 6.3.9 Port Status and Control Register

84 6.3.10 Port PM Status and Control Register (USB 3.0 Ports)85 6.3.11 Port PM Status and Control Register (USB 2.0 Ports)86 6.3.12 Port Link Info Register

86 6.4 Host Controller Runtime Registers

87 6.4.1 Microframe Index Register

87 6.4.2 Interrupter Management Register

88 6.4.3 Interrupter Moderation Register

88 6.4.4 Event Ring Segment Table Size Register

89 6.4.5 Event Ring Segment Table Base Address Register

89 6.4.6 Event Ring Dequeue Pointer Register

90 6.5 Host Controller Doorbell Registers

91 6.6 xHCI Extended Capabilities Registers

91 6.6.1 USB Legacy Support Capability Register

91 6.6.2 USB Legacy Support Control/Status Register

92 6.6.3 xHCI Supported Protocol Capability Register (USB 2.0)93 6.6.4 xHCI Supported Protocol Name String Register (USB 2.0)93 6.6.5 xHCI Supported Protocol Port Register (USB 2.0)94 6.6.6 xHCI Supported Protocol Capability Register (USB 3.0)94 6.6.7 xHCI Supported Protocol Name String Register (USB 3.0)95 6.6.8 xHCI Supported Protocol Port Register (USB 3.0)95

7 MSI-X MEMORY MAPPED REGISTER SPACE

97 7.1 The MSI-X Table and PBA in Memory Mapped Register Space

97 8 PHY CONTROL

98 8.1 Output Voltage Swing Control

98 8.2 De-Emphasis Control

99 8.3 Adaptive Equalizer

99 9 INPUT CLOCK

101 9.1 Clock Source Requirements

101 9.2 External clock

102 9.3 External crystal

102 10 PCI EXPRESS POWER MANAGEMENT

103 10.1 Power Management

103 10.2 PCI Express Link Power Management States

103 10.3 PCI Express Power Management D-States

103 4 Contents Copyright ? 2011C2013, Texas Instruments Incorporated TUSB7320, TUSB7340 www.ti.com SLLSE76L CMARCH 2011CREVISED MAY