PDF《USB 3.0 xHCI HOST CONTROLLER》

TUSB7320, TUSB7340 USB 3.

0 xHCI HOST CONTROLLER Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLLSE76L March 2011CRevised May

2013 TUSB7320, TUSB7340 www.ti.com SLLSE76L CMARCH 2011CREVISED MAY

2013 Contents

1 INTRODUCTION

12 1.1 Features

12 1.2 Target Applications

12 2 OVERVIEW

13 2.1 Description

13 2.2 Related Documents

14 2.3 Document'

s Conventions

14 2.4 Available Options

14 2.5 ORDERING INFORMATION

14 2.6 Terminal Assignments

15 2.7 Terminal Descriptions

17 3 FEATURE/PROTOCOL DESCRIPTIONS

21 3.1 Power-Up/-Down Sequencing

21 3.1.1 Power-Up Sequence

21 3.1.2 Power-Down Sequence

22 3.2 Two-Wire Serial-Bus Interface

22 3.2.1 Serial-Bus Interface Implementation

22 3.2.2 Serial-Bus Interface Protocol

24 3.2.3 Serial-Bus EEPROM Application

26 3.3 System Management Interrupt

27 4 CLASSIC PCI CONFIGURATION SPACE

28 4.1 The PCI Configuration Map

28 4.2 Vendor ID Register

29 4.3 Device ID Register

29 4.4 Command Register

30 4.5 Status Register

31 4.6 Class Code and Revision ID Register

32 4.7 Cache Line Size Register

32 4.8 Latency Timer Register

33 4.9 Header Type Register

33 4.10 BIST Register

33 4.11 Base Address Register

0 34 4.12 Base Address Register

1 34 4.13 Base Address Register

2 35 4.14 Base Address Register

3 35 4.15 Subsystem Vendor ID Register

36 4.16 Subsystem ID Register

36 4.17 Capabilities Pointer Register

36 4.18 Interrupt Line Register

37 4.19 Interrupt Pin Register

37 4.20 Min Grant Register

37 4.21 Max Latency Register

37 4.22 Capability ID Register

38 4.23 Next Item Pointer Register

38 4.24 Power Management Capabilities Register

38 4.25 Power Management Control/Status Register

39 4.26 Power Management Bridge Support Extension Register

39 4.27 Power Management Data Register

40 4.28 MSI Capability ID Register

40 4.29 Next Item Pointer Register

40 4.30 MSI Message Control Register

40 2 Contents Copyright ? 2011C2013, Texas Instruments Incorporated TUSB7320, TUSB7340 www.ti.com SLLSE76L CMARCH 2011CREVISED MAY

2013 4.31 MSI Lower Message Address Register

41 4.32 MSI Upper Message Address Register

42 4.33 MSI Message Data Register

42 4.34 Serial Bus Release Number Register (SBRN)43 4.35 Frame Length Adjustment Register (FLADJ)43 4.36 PCI Express Capability ID Register

43 4.37 Next Item Pointer Register

44 4.38 PCI Express Capabilities Register

44 4.39 Device Capabilities Register

45 4.40 Device Control Register

46 4.41 Device Status Register

47 4.42 Link Capabilities Register

47 4.43 Link Control Register

48 4.44 Link Status Register

49 4.45 Device Capabilities

2 Register

49 4.46 Device Control

2 Register

50 4.47 Link Control

2 Register

50 4.48 Link Status

2 Register

51 4.49 Serial Bus Data Register

51 4.50 Serial Bus Index Register

52 4.51 Serial Bus Slave Address Regsiter

52 4.52 Serial Bus Control and Status Register

52 4.53 GPIO Control Register

53 4.54 GPIO Data Register

54 4.55 MSI-X Capability ID Register

55 4.56 Next Item Pointer Register

55 4.57 MSI-X Message Control Register

55 4.58 MSI-X Table Offset and BIR Register

56 4.59 MSI-X PBA Offset and BIR Register

56 4.60 Subsystem Access Register

57 4.61 General Control

0 Register