编辑: yn灬不离不弃灬 2019-07-06

1 2

3 4

5 6

7 8 add r3, r1, r2 sub r5, r3, r5 or r6, r3, r4 add r6, r3, r8 IF ID11=r122=r2 EXD=33 MEMD=33 WB r3=33 IF ID ?=r3 ID ?=r3 ID ?=r3 ID 33=r3 EX MEM WB IF IF IF IF ID 33=r3 EX M IF ID 33=r3 EX r3 =

10 r3 =

20 time IF ID Ex M W IF ID Ex M W IF ID Ex M ID ID ID IF IF IF IF ID Ex Stalls

3 Stall Stalling datamem B A B D M D instmem DrD B A Rd Rd Rd WE WE Op WE Op rA rB PC Op nop inst /stall add r3,r1,r2 (MemWr=0 RegWr=0) NOP = If(IF/ID.rA ≠

0 &

&

(IF/ID.rA==ID/Ex.Rd IF/ID.rA==Ex/M.Rd IF/ID.rA==M/W.Rd)) sub r5,r3,r5 or r6,r3,r4 (WE=0) Stalling datamem B A B D M D instmem DrD B A Rd Rd Rd WE WE Op WE Op rA rB PC Op nop inst /stall nop (MemWr=0 RegWr=0) NOP = If(IF/ID.rA ≠

0 &

&

(IF/ID.rA==ID/Ex.Rd IF/ID.rA==Ex/M.Rd IF/ID.rA==M/W.Rd)) add r3,r1,r2 sub r5,r3,r5 (MemWr=0 RegWr=0) or r6,r3,r4 (WE=0) Stalling datamem B A B D M D instmem DrD B A Rd Rd Rd WE WE Op WE Op rA rB PC Op nop inst /stall (MemWr=0 RegWr=0) NOP = If(IF/ID.rA ≠

0 &

&

(IF/ID.rA==ID/Ex.Rd IF/ID.rA==Ex/M.Rd IF/ID.rA==M/W.Rd)) add r3,r1,r2 sub r5,r3,r5 nop nop (MemWr=0 RegWr=0) (MemWr=0 RegWr=0) or r6,r3,r4 (WE=0) Stalling How to stall an instruction in ID stage prevent IF/ID pipeline register update stalls the ID stage instruction convert ID stage instr into nop for later stages innocuous bubble passes through pipeline prevent PC update stalls the next (IF stage) instruction Forwarding Forwarding bypasses some pipelined stages forwarding a result to a dependent instruction operand (register). Three types of forwarding/bypass Forwarding from Ex/Mem registers to Ex stage (M?Ex) Forwarding from Mem/WB register to Ex stage (W?Ex) RegisterFile Bypass Forwarding Datapath datamem imm B A B D M D instmem Rd Rd Rb WE WE MC Ra MC forwardunit detecthazard Three types of forwarding/bypass Forwarding from Ex/Mem registers to Ex stage (M?Ex) Forwarding from Mem/WB register to Ex stage (W ? Ex) RegisterFile Bypass IF/ID ID/Ex Ex/Mem Mem/WB Forwarding Datapath Ex/MEM to EX Bypass EX needs ALU result that is still in MEM stage Resolve: Add a bypass from EX/MEM.D to start of EX How to detect? Logic in Ex Stage: forward = (Ex/M.WE &

&

EX/M.Rd !=

0 &

&

ID/Ex.Ra == Ex/M.Rd) || (same for rB) earlier = started earlier = stage right stage left destination reg of earlier instruction == source reg of current ........

下载(注:源文件不在本站服务器,都将跳转到源网站下载)
备用下载
发帖评论
相关话题
发布一个新话题