PDF《STM32F303xB/C Errata sheet》

17 2.4.5 Wakeup frame may not wakeup from STOP if tHD(STA) is close to tsu(HSI) in Fast-mode and Fast-mode Plus.18 2.4.6 Wrong data sampling when data set-up time (tSU;

DAT) is smaller than one I2CCLK period

18 2.4.7 Spurious bus error detection in master mode

19 2.5 USART limitations

19 2.5.1 Communication parameters reprogramming after ATR in Smartcard mode when SCLK is used to clock the card

19 2.5.2 Last byte written in TDR might not be transmitted if TE is cleared just after writing in TDR.19 2.5.3 Start bit detected too soon when sampling for NACK signal from the smartcard

20 2.5.4 Break request can prevent the Transmission Complete flag (TC) from being set

20 2.5.5 nRTS is active while RE or UE =

0 20 2.5.6 Receiver timeout counter starting in case of a

2 stop bit configuration .

21 2.6 I2S peripheral limitations

21 2.6.1 In I2S slave mode, WS level must be set by the external master when enabling the I2S

21 2.7 TIM peripheral limitations

21 2.7.1 Spurious break generation during TIM1/TIM8 BRK2 initialization

21 2.8 GPIO peripheral limitation

22 2.8.1 GPIOx locking mechanism is not working properly for GPIOx_OTYPE register

22 2.9 Comparator peripheral limitation

22 2.9.1 VREFINT scaler startup time from power down parameter degradation

22 3 Revision history

23 List of tables STM32F303xB/C 4/25 DocID023637 Rev

9 List of tables Table 1. Device identification

1 Table 2. Device summary

1 Table 3. Cortex? -M4 with FPU limitations and impact on microcontroller behavior

5 Table 4. Summary of silicon limitations

7 Table 5. Document revision history

23 DocID023637 Rev

9 5/25 STM32F303xB/C ARM? 32-bit Cortex?-M4 with FPU limitations

24 1 ARM? 32-bit Cortex?-M4 with FPU limitations An errata notice of the STM32F3xx core is available from the following web address: http://infocenter.arm.com. All the described limitations are minor and related to the revision r0p1-v1 of the Cortex? -M4 with FPU. Table

3 summarizes these limitations and their implications on the behavior of STM32F30xxx devices. 1.1 Cortex?-M4 with FPU interrupted loads to stack pointer can cause erroneous behavior Description An interrupt occurring during the data-phase of a single word load to the stack pointer (SP/R13) can cause an erroneous behavior of the device. In addition, returning from the interrupt results in the load instruction being executed with an additional time. For all the instructions performing an update of the base register, the base register is erroneously updated on each execution, resulting in the stack pointer being loaded from an incorrect memory location. The instructions affected by this limitation are the following: ? LDR SP, [Rn],#imm ? LDR SP, [Rn,#imm]! ? LDR SP, [Rn,#imm] ? LDR SP, [Rn] ? LDR SP, [Rn,Rm] Workaround As of today, no compiler generates these particular instructions. This limitation can only occur with hand-written assembly code. Both issues can be solved by replacing the direct load to the stack pointer by an intermediate load to a general-purpose register followed by a move to the stack pointer. Example: Replace LDR SP, [R0] by LDR R2,[R0] MOV SP,R2 Table 3. Cortex? -M4 with FPU limitations and impact on microcontroller behavior ARM ID ARM category ARM summary of errata Impact on STM32F30xxx

752770 Cat B Interrupted loads to SP can cause erroneous behavior Minor

776924 Cat B VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Minor ARM? 32-bit Cortex?-M4 with FPU limitations STM32F303xB/C 6/25 DocID023637 Rev