PDF《DATA SHEET》

DATA SHEET Product speci?cation Supersedes data of September

1993 File under Integrated Circuits, IC06

1998 Sep

30 INTEGRATED CIRCUITS 74HC/HCT257 Quad 2-input multiplexer;

3-state For a complete data sheet, please also download: ? The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications ? The IC06 74HC/HCT/HCU/HCMOS Logic Package Information ? The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

1998 Sep

30 2 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 FEATURES ? Non-inverting data path ? 3-state outputs interface directly with system bus ? Output capability: bus driver ? ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT257 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT257 have four identical 2-input multiplexers with 3-state outputs, which select

4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source

0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source

1 (1I1 to 4I1) are selected when S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The

257 is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH. The logic equations for the outputs are: 1Y = OE.(1I1.S + 1I0.S) 2Y = OE.(2I1.S + 2I0.S) 3Y = OE.(3I1.S + 3I0.S) 4Y = OE.(4I1.S + 4I0.S) The

257 is identical to the

258 but has non-inverting (true) outputs. QUICK REFERENCE DATA GND =

0 V;

Tamb =

25 °C;

tr = tf =

6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in ?W): PD = CPD * VCC

2 * fi + ∑ (CL * VCC

2 * fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL * VCC

2 * fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC ? 1.5 V SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay CL =

15 pF;

VCC =

5 V nI0, nI1 to nY

11 13 ns S to nY

14 17 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per multiplexer notes

1 and

2 45

45 pF

1998 Sep

30 3 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 ORDERING INFORMATION PIN DESCRIPTION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION 74HC257N;

74HCT257N DIP16 plastic dual in-line package;

16 leads (300 mil);

long body SOT38-1 74HC257D;

74HCT257D SO16 plastic small outline package;

16 leads;

body width 3.9 mm SOT109-1 74HC257DB;

74HCT257DB SSOP16 plastic shrink small outline package;

16 leads;

body width 5.3 mm SOT338-1 74HC257PW;

74HCT257PW TSSOP16 plastic thin shrink small outline package;

16 leads;

body width 4.4 mm SOT403-1 PIN NO. SYMBOL NAME AND FUNCTION

1 S common data select input 2, 5, 11,

14 1I0 to 4I0 data inputs from source

0 3, 6, 10,

13 1I1 to 4I1 data inputs from source

1 4, 7, 9,

12 1Y to 4Y 3-state multiplexer outputs

8 GND ground (0 V)

15 OE 3-state output enable input (active LOW)

16 VCC positive supply voltage Fig.1 Pin configuration. fpage GND VCC MLB311 S OE 1Y 2Y 4Y 3Y

1 2

3 4

5 6

7 8

16 15

14 13

12 11

10 9

257 1I0 1I1 2I0 2I1 4I0 4I1 3I0 3I1 Fig.2 Logic symbol. fpage MGA835 S OE 1Y 2Y 3Y 4Y

2 3

5 6

11 10

14 13

15 1

4 7

9 12 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 Fig.3 IEC logic symbol.

1998 Sep

30 4 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 Fig.4 Functional diagram. MGR280 S

1 1I0

2 1Y

4 1I1

3 SELECTOR 3-STATE MULTIPLEXER OUTPUTS 2I0

5 2Y

7 2I1

6 3I0

11 3Y

12 3I1

10 4I0

14 4Y

9 4I1

13 OE

15 FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don'

t care Z = high impedance OFF-state INPUTS OUTPUT OE S nI0 nI1 nY H X X X Z L H X L L L H X H H L L L X L L L H X H Fig.5 Logic diagram.

1998 Sep

30 5 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications . Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND =

0 V;

tr = tf =

6 ns;

CL =

50 pF SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS +25 ?40 to +85 ?40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay nI0 to nY;

nI1 to nY

36 110

140 165 ns 2.0 Fig.6

13 22

28 33 4.5

10 19

24 28 6.0 tPHL/ tPLH propagation delay S to nY

47 150

190 225 ns 2.0 Fig.6

17 30

38 45 4.5

14 26

33 38 6.0 tPZH/ tPZL 3-state output enable time OE to nY

33 150

190 225 ns 2.0 Fig.7

12 30

38 45 4.5

10 26

33 38 6.0 tPHZ/ tPLZ 3-state output disable time OE to nY

41 150

190 225 ns 2.0 Fig.7

15 30

38 45 4.5

12 26

33 38 6.0 tTHL/ tTLH output transition time

14 60

75 90 ns 2.0 Fig.6

5 12

15 18 4.5

4 10

13 15 6.0

1998 Sep

30 6 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications . Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (?ICC) for a unit load of

1 is given in the family specifications. To determine ?ICC per input, multiply this value by the unit load coefficient shown in the table below. AC CHARACTERISTICS FOR 74HCT GND =

0 V;

tr = tf =

6 ns;

CL =

50 pF INPUT UNIT LOAD COEFFICIENT nI0 0.40 nI1 0.40 OE 1.35 S 0.70 SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS +25 ?40 to +85 ?40 to +125 min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay

16 30

38 45 ns 4.5 Fig.6 nI0 to nY nI1 to nY tPHL/ tPLH propagation delay S to nY

20 35

44 53 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time OE to nY

15 30

38 45 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time OE to nY

16 30

38 45 ns 4.5 Fig.7 tTHL/ tTLH output transition time

5 12

15 18 ns 4.5 Fig.6

1998 Sep

30 7 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 AC WAVEFORMS Fig.6 Waveforms showing the input (nI0, nI1) to output (nY) propagation delays and the output transition times. (1) HC: VM = 50%;

VI = GND to VCC. HCT: VM = 1.3 V;

VI = GND to

3 V. Fig.7 Waveforms showing the 3-state enable and disable times. (1) HC: VM = 50%;

VI = GND to VCC. HCT: VM = 1.3 V;

VI = GND to

3 V.

1998 Sep

30 8 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 PACKAGE OUTLINES UNIT A max.

1 2 b1 c E e MH L REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT38-1 92-10-02 95-01-19 A min. A max. b max. w ME e1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.30 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.10 0.020 0.19 050G09 MO-001AE MH c (e )

1 ME A L seating plane A1 w M b1 e D A2 Z

16 1

9 8 b E pin

1 index

0 5

10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) D (1) Z DIP16: plastic dual in-line package;

16 leads (300 mil);

long body SOT38-1

1998 Sep

30 9 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 X w M θ A A1 A2 bp D HE Lp Q detail X E Z e c L v M A (A )

3 A

8 9

1 16 y pin

1 index UNIT A max. A1 A2 A3 bp c D(1) E(1) (1) e HE L Lp Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3

8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 SOT109-1 95-01-23 97-05-22 076E07S MS-012AC 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016

0 2.5

5 mm scale SO16: plastic small outline package;

16 leads;

body width 3.9 mm SOT109-1

1998 Sep

30 10 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 UNIT A1 A2 A3 bp c D(1) E (1) e HE L Lp Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55

8 0 o o 0.13 0.2 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT338-1 94-01-14 95-02-04 (1) w M bp D HE E Z e c v M A X A y

1 8

16 9 θ A A1 A2 Lp Q detail X L (A )

3 MO-150AC pin

1 index

0 2.5

5 mm scale SSOP16: plastic shrink small outline package;

16 leads;

body width 5.3 mm SOT338-1 A max. 2.0

1998 Sep

30 11 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 UNIT A1 A2 A3 bp c D (1) E (2) (1) e HE L Lp Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06

8 0 o o 0.13 0.1 0.2 1.0 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 94-07-12 95-04-04 w M bp D Z e 0.25

1 8

16 9 θ A A1 A2 Lp Q detail X L (A )

3 HE E c v M A X A y

0 2.5

5 mm scale TSSOP16: plastic thin shrink small outline package;

16 leads;

body width 4.4 mm SOT403-1 A max. 1.10 pin

1 index

1998 Sep

30 12 Philips Semiconductors Product speci?cation Quad 2-input multiplexer;

3-state 74HC/HCT257 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26;

Integrated Circuit Packages (order code

9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximu........