PDF《SCDS356C – NOVEMBER 2014 – REVISED》

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers.

PRODUCTION DATA. TS3DDR4000 SCDS356C CNOVEMBER 2014CREVISED MARCH

2019 TS3DDR4000 12-bits 1:2 high speed DDR2/DDR3/DDR4 switch/multiplexer

1 1 Features 1? Wide VDD Range: 2.375 V C 3.6 V ? High Bandwidth: 5.6 GHz Typical (single-ended);

6.0 GHz Typical (differential) ? Low Switch On-Resistance (RON):

8 ? Typical ? Low Bit-to-Bit Skew: 3ps Typical;

6ps Max across All Channels ? Low Crosstalk: C34 dB Typical at

1067 MHz ? Low Operating Current:

40 ?A Typical ? Low-Power Mode with Low Current Consumption:

2 ?A Typical ? IOFF Protection Prevents Current Leakage in Powered Down State (VDD =

0 V) ? Supports POD_12, SSTL_12, SSTL_15 and SSTL_18 Signaling ? ESD Performance: C 3-kV Human Body Model (A114B, Class II) C 1-kV Charged Device Model (C101) ?

8 mm x

3 mm 48-balls 0.65-mm Pitch ZBA Package

2 Applications ? NVDIMM Modules ? Enterprise Data Systems and Servers ? Notebook/Desktop PCs ? General DDR3/DDR4 Signal Switching ? General High-Speed Signal Switching

3 Description The TS3DDR4000 is 1:2 or 2:1 high speed DDR2/DDR3/DDR4 switch that offers 12-bit wide bus switching. The A port can be switched to the B or C port for all bits simultaneously. Designed for operation in DDR2, DDR3 and DDR4 memory bus systems, the TS3DDR4000 uses a proprietary architecture that delivers high bandwidth (single-ended C3dB bandwidth at 5.6 GHz), low insertion loss at low frequency, and very low propagation delay. The TS3DDR4000 is 1.8 V logic compatible, and all switches are bi-directional for added design flexibility. The TS3DDR4000 also offers a low-power mode, in which all channels become high-Z and the device consumes minimal power. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TS3DDR4000 NFBGA (48) 8.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Application Diagram

2 TS3DDR4000 SCDS356C CNOVEMBER 2014CREVISED MARCH

2019 www.ti.com Product Folder Links: TS3DDR4000 Submit Documentation Feedback Copyright ? 2014C2019, Texas Instruments Incorporated Table of Contents

1 Features.1

2 Applications

1 3 Description

1 4 Revision History.2

5 Pin Configuration and Functions.3

6 Specifications.4 6.1 Absolute Maximum Ratings

4 6.2 ESD Ratings.4 6.3 Recommended Operating Conditions.4 6.4 Thermal Information.4 6.5 Static Electrical Characteristics.5 6.6 Dynamic Electrical Characteristics.6 6.7 Typical Characteristics.7

7 Parameter Measurement Information

9 8 Detailed Description

11 8.1 Overview

11 8.2 Functional Block Diagram

11 8.3 Feature Description.12 8.4 Device Functional Modes.12

9 Application and Implementation

13 9.1 Application Information.13 9.2 Typical Application

13 10 Power Supply Recommendations

14 11 Layout.15 11.1 Layout Guidelines

15 11.2 Layout Example

16 12 Device and Documentation Support

17 12.1 Receiving Notification of Documentation Updates

17 12.2 Community Resources.17 12.3 Trademarks.17 12.4 Electrostatic Discharge Caution.17 12.5 Glossary.17

13 Mechanical, Packaging, and Orderable Information

17 4 Revision History Changes from Revision B (May 2017) to Revision C Page ? Changed the Pin Configuration image.3 ? Changed VIH From: SEL1m and SEL2 To: SEL0 and SEL1 with a MIN value of

1 V in the Recommended Operating Conditions.4 ? Changed SEL1 To: SEL0 and SLE2 To: SEL1 in Figure 18.11 ? Changed text '

Standard layout technique for 0.5 mm pitch BGA package To: Standard layout technique for 0.65 mm pitch BGA package... in the Layout Guidelines.15 Changes from Revision A (March 2015) to Revision B Page ? Changed VDD Max value From: 5.5 V toTo: 4.8 V in the Absolute Maximum Ratings.4 ? Added the Note to the Application and Implementation section.13 Changes from Original (November 2014) to Revision A Page ? Updated document to full version.1

3 TS3DDR4000 www.ti.com SCDS356C CNOVEMBER 2014CREVISED MARCH

2019 Product Folder Links: TS3DDR4000 Submit Documentation Feedback Copyright ? 2014C2019, Texas Instruments Incorporated

5 Pin Configuration and Functions ZBA Package 48-Balls (NFBGA) Top View Pin Functions PINS TYPE DESCRIPTION NAME NO. VDD C2, G2, K2 Power Power supply GND B2, D2, E2, F2, J2, L2 Ground Ground A0-A11 A1-M1 I/O Port A, signal 0-11 B0-B11 A3-M3 I/O Port B, signal 0-11 C0-C11 A4-M4 I/O Port C, signal 0-11 SEL0 A2 I Select control

0 SEL1 M2 I Select control

1 EN H2 I Enable

4 TS3DDR4000 SCDS356C CNOVEMBER 2014CREVISED MARCH

2019 www.ti.com Product Folder Links: TS3DDR4000 Submit Documentation Feedback Copyright ? 2014C2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Voltage range on VDD -0.3 4.8 V VIN Control input voltage range: SEL0, SEL1, and /EN -0.3 5.5 V VI/O Analog voltage range: A0-A11, B0-B11, and C0-C11 -0.3 3.6 V TA Operating ambient temperature range -40

85 °C Tstg Storage temperature range -65

125 °C (1) Tested in accordance with JEDEC Standard 22, Test Method C101 (2) Tested in accordance with JEDEC Standard 22, Test Method A114 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Charge device model (CDM)(1) ±1000 V Human body model (HBM) on all pins(2) ±3000 V 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD Voltage range on VDD 2.375 3.6 V VI/O Analog voltage range: A0-A11, B0-B11, and C0-C11

0 3.3 V VIH High-level control input voltage threshold (EN) 1.4 VDD V High-level control input voltage threshold (SEL0 and SEL1)

1 VDD V VIL Low-level control input voltage threshold (EN, SEL0 and SEL1)

0 0.5 V TA Operating ambient temperature range -40

85 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report . 6.4 Thermal Information THERMAL METRIC(1) TS3DDR4000 UNIT BGA (48) RθJA Junction-to-ambient thermal resistance 92.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 33.4 RθJB Junction-to-board thermal resistance 56.2 ψJT Junction-to-top characterization parameter 1.3 ψJB Junction-to-board characterization parameter 54.9

5 TS3DDR4000 www.ti.com SCDS356C CNOVEMBER 2014CREVISED MARCH

2019 Product Folder Links: TS3DDR4000 Submit Documentation Feedback Copyright ? 2014C2019, Texas Instruments Incorporated 6.5 Static Electrical Characteristics Unless otherwise noted the specification applies over the VDD range and operation junction temp of C40°C ≤ TJ ≤ 85°C. Typical values are for VDD = 3.3 V and TJ = 25°C. PARAMETER TEST CONDITION MIN TYP MAX UNIT RON On-state resistance Port A to B VDD = 2.375 V, VI/O = 1.2 V, II/O =

10 mA C 8.3 11.2 Ω Port A to C C 8.3 11.2 Ω RON (FLAT) On-state resistance flatness for all I/Os Port A to B VDD = 2.375 V, VI/O = 1.2 V, II/O =

10 mA C 0.6 C Ω Port A to C C 0.6 C Ω ?RON On-state resistance match between channels Port A to B VDD = 2.375 V, VI/O = 1.2 V, II/O =

10 mA C 0.2 1.0 Ω Port A to C C 0.2 1.0 Ω IIH Control input high leakage current EN VDD = 3.6 V, V/EN = 1.4 V C C ±1 ?A VDD = 2.375 V, V/EN = 3.3 V C C ±1 ?A SEL1 VDD = 3.6 V, VSEL1 = 1.4 V C C ±1 ?A VDD = 2.375 V, VSEL1 = 3.3 V C C ±1 ?A SEL2 VDD = 3.6 V, VSEL2 = 1.4 V C C ±1 ?A VDD = 2.375 V, VSEL2 = 3.3 V C C ±1 ?A IIL Control input low leakage current EN VDD = 3.6 V, V/EN =

0 V C C ±0.5 ?A SEL1 VDD = 3.6 V, VSEL1 =

0 V C C ±0.5 ?A SEL2 VDD = 3.6 V, VSEL2 =

0 V C C ±0.5 ?A IOFF Leakage under power off condition for all I/Os EN VDD =

0 V, V/EN =

0 V, VI/O =

0 V to 3.3 V C C ±5 ?A VDD =

0 V, V//EN = 3.6 V, VI/O =

0 V to 3.3 V C C ±5 ?A SEL1 VDD =

0 V, VSEL1 =

0 V, VI/O =

0 V to 3.3 V C C ±5 ?A VDD =

0 V, VSEL1 = 3.6 V, VI/O =

0 V to 3.3 V C C ±5 ?A SEL2 VDD =

0 V, VSEL2 =

0 V, VI/O =

0 V to 3.3 V C C ±5 ?A VDD =

0 V, VSEL2 = 3.6 V, VI/O =

0 V to 3.3 V C C ±5 ?A IDD VDD supply current VDD = 3.6 V, II/O =

0 A, /EN =

0 V, VSEL1 = VSEL2=

0 V C

28 35 ?A VDD = 3.6 V, II/O =

0 A, /EN =

0 V, VSEL1 = VSEL2= 1.8 V C

40 48 ?A VDD = 3.6 V, II/O =

0 A, /EN =

0 V, VSEL1 =

0 V, VSEL2= 1.8 V C

40 44 ?A VDD = 3.6 V,II/O =

0 A, /EN =

0 V, VSEL1 = 1.8 V, VSEL2=

0 V C

40 44 ?A IDD, PD VDD supply current in power-down mode VDD = 3.6 V, II/O =

0 A, /EN = 1.8 V C

2 5 ?A

6 TS3DDR4000 SCDS356C CNOVEMBER 2014CREVISED MARCH

2019 www.ti.com Product Folder Links: TS3DDR4000 Submit Documentation Feedback Copyright ? 2014C2019, Texas Instruments Incorporated (1) Verified by design. 6.6 Dynamic Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT tON Switch turn-on time EN to B VDD = 2.375 V, RL =

50 Ω, VAn = 3.3 V, V/EN = 1.8 V→

0 V, VSEL1 = VSEL2 =

0 V (See Figure 12) C

65 140 ?s EN to C VDD = 2.375 V, RL =

50 Ω, VAn = 3.3 V, V/EN = 1.8 V→

0 V, VSEL1 = VSEL2 = 1.8 V (See Figure 12) C

65 140 ?s tSWITCH Switching time between channels for all I/Os SEL to B VDD = 2.375 V, V/EN =

0 V, RL =

50 Ω, VAn = 3.3 V, (See Figure 13) C

65 C ns SEL to C VDD = 2.375 V, V/EN =

0 V, RL =

50 Ω, VAn = 3.3 V, (See Figure 13) C

50 C ns tPD Propagation delay Port A to B VDD = 2.375 V, (See Figure 14) C

85 C ps Port A to C VDD = 2.375 V, (See Figure 14) C

85 C ps tSKEW (1) Singe-ended skew between channels B0 to B11 VDD = 2.375 V, from any output to any other output C

3 8 ps C0 to C11 C

3 6 ps CIN Control input capacitance EN f =

1 MHz, VIN=

0 V C

6 C pF SEL1 f =

1 MHz, VIN=

0 V C

6 C pF SEL2 f =

1 MHz, VIN=

0 V C

6 C pF COFF Switch off capacitance Port A to B f =

1067 MHz, VI/O =

0 V, VSEL1 = VSEL2 = 1.8V C 0.5 C pF Port A to C f =

1067 MHz, VI/O =

0 V, VSEL1 = VSEL2 =

0 V C 0.5 C pF CON Switch on capacitance Port A to B f =

1067 MHz, VI/O = 1.2 V........