PDF《8-bit》

Features ? High Performance, Low Power AVR? 8-Bit Microcontroller ? Advanced RISC Architecture C

120 Powerful Instructions C Most Single Clock Cycle Execution C

32 x

8 General Purpose Working Registers C Fully Static Operation C Up to

20 MIPS Througput at

20 MHz ? High Endurance Non-volatile Memory segments C 1K Bytes of In-System Self-programmable Flash program memory C

64 Bytes EEPROM C

64 Bytes Internal SRAM C Write/Erase Cycles: 10,000 Flash/100,000 EEPROM C Data retention:

20 Years at 85°C/100 Years at 25°C (see page 6) C Programming Lock for Self-Programming Flash &

EEPROM Data Security ? Peripheral Features C One 8-bit Timer/Counter with Prescaler and Two PWM Channels C 4-channel, 10-bit ADC with Internal Voltage Reference C Programmable Watchdog Timer with Separate On-chip Oscillator C On-chip Analog Comparator ? Special Microcontroller Features C debugWIRE On-chip Debug System C In-System Programmable via SPI Port C External and Internal Interrupt Sources C Low Power Idle, ADC Noise Reduction, and Power-down Modes C Enhanced Power-on Reset Circuit C Programmable Brown-out Detection Circuit with Software Disable Function C Internal Calibrated Oscillator ? I/O and Packages C 8-pin PDIP/SOIC: Six Programmable I/O Lines C 10-pad MLF: Six Programmable I/O Lines C 20-pad MLF: Six Programmable I/O Lines ? Operating Voltage: C 1.

8 C 5.5V ? Speed Grade: C

0 C

4 MHz @ 1.8 C 5.5V C

0 C

10 MHz @ 2.7 C 5.5V C

0 C

20 MHz @ 4.5 C 5.5V ? Industrial Temperature Range ? Low Power Consumption C Active Mode: ?

190 ?A at 1.8 V and

1 MHz C Idle Mode: ?

24 ?A at 1.8 V and

1 MHz 8-bit Microcontroller with 1K Bytes In-System Programmable Flash ATtiny13A Summary Rev. 8126FSCAVRC05/12

2 8126FSCAVRC05/12 ATtiny13A 1. Pin Configurations Figure 1-1. Pinout of ATtiny13A

1 2

3 4

8 7

6 5 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 GND VCC PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) 8-PDIP/SOIC

1 2

3 4

5 20-QFN/MLF

15 14

13 12

11 20

19 18

17 16

6 7

8 9

10 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 DNC DNC (PCINT4/ADC2) PB4 DNC DNC GND DNC DNC VCC PB2 (SCK/ADC1/T0/PCINT2) DNC PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) DNC DNC DNC DNC DNC NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect

1 2

3 4

5 10-QFN/MLF

10 9

8 7

6 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 DNC (PCINT4/ADC2) PB4 GND VCC PB2 (SCK/ADC1/T0/PCINT2) DNC PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect

3 8126FSCAVRC05/12 ATtiny13A 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13A as listed on page 55. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min- imum pulse length is given in Table 18-4 on page 120. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin.