PDF《STM32F303xD STM32F303xE Errata sheet》

December

2018 ES0261 Rev

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1 STM32F303xD STM32F303xE Errata sheet STM32F303xD STM32F303xE Rev Y device limitations Silicon identification This errata sheet applies to revision Y of STMicroelectronics STM32F303xD/xE products.

These products feature an Arm? 32-bit Cortex? -M4 core with FPU, for which an errata notice is also available (see Section

1 for details). Section

2 gives a detailed description of the product silicon limitations. The products are identifiable as shown in Table 1: ? By the revision code marked below the order code on the device package. ? By the last three digits of the internal order code printed on the box label. The full list of part numbers is shown in Table 2. Table 1. Device identification(1) 1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the STM32F303xx and STM32F3x8xx reference manual for details on how to find the revision code). Sales type Revision code(2) marked on device 2. Refer to STM32F303xD/xE datasheet for the device marking. STM32F303xD/xE Y Table 2. Device summary Reference Part number STM32F303xD STM32F303RD, STM32F303VD, STM32F303ZD STM32F303xE STM32F303RE, STM32F303VE, STM32F303ZE www.st.com Contents STM32F303xD STM32F303xE 2/21 ES0261 Rev

5 Contents

1 Arm? 32-bit Cortex?-M4 core with FPU limitations

5 1.1 Cortex?-M4 core with FPU interrupted loads to stack pointer can cause erroneous behavior

5 2 STM32F303xD/xE silicon limitations

7 2.1 System limitations

8 2.1.1 Wakeup sequence from Standby mode when using more than one wakeup source

8 2.1.2 Minimum CPU frequency and prefetch buffer state

9 2.1.3 Full JTAG configuration without NJTRST pin cannot be used

9 2.1.4 No reset of CCM RAM write protection register SYSCFG_RCR by system reset

9 2.2 ADC peripheral limitations

10 2.2.1 DMA Overrun in dual interleaved mode with single DMA channel . . . .

10 2.2.2 Overrun flag may not be set if converted data are not read before writing new data

10 2.2.3 Sampling time shortened in JAUTO autodelayed mode

10 2.2.4 Injected queue of context is not available in case of JQM =

0 10 2.2.5 Multiple Loads not supported by ADC interface

11 2.2.6 ADC differential mode, common mode input range

11 2.3 Comparator limitations

11 2.4 OPAMP limitations

11 2.4.1 OPAMP Timer controlled multiplexer mode not working when OPAMP is used in PGA or follower mode

11 2.5 SPI peripheral limitations

12 2.5.1 SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI, is under DMA transaction near the end of transfer or end of transfer '

-1'

12 2.5.2 BSY bit may stay high at the end of a SPI data transfer in slave mode .

12 2.6 I2 C peripheral limitations

13 2.6.1 10-bit slave mode: wrong direction bit value after Read header reception

13 2.6.2 10-bit combined with 7-bit slave mode: ADDCODE may indicate wrong slave address detection

13 2.6.3 Wakeup frames may not wakeup the MCU mode when STOP mode entry follows I2 C enabling

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3 2.6.4 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by I2 C peripheral is disabled

15 2.6.5 Wakeup frame may not wakeup from STOP if tHD(STA) is close to tsu(HSI) in Fast-mode and Fast-mode Plus

15 2.6.6 Spurious Bus Error detection in master mode

16 2.7 I2 S limitations

16 2.7.1 In I2 S slave mode, WS level must be set by the external master when enabling the I2 S

16 2.8 Timer limitations

17 2.8.1 TIM20 Brk2 acts to COMPx_OUT even if COMPx_OUT is configured to be connected internally to TIM1 and TIM8 Brk2 only